Video display systems based on spatial light modulators (SLMs) are increasingly being used as an alternative to display systems using cathode ray tubes (CRTs). SLM systems provide high resolution displays without the bulk and power consumption of CRT systems.
Digital micro-mirror devices (DMDs) are a type of SLM, and may be used for projection display applications. The images provided by a DMD compare favorably with those provided by CRTs and can be projected to a screen in dimensions surpassing today's large screen televisions.
A DMD has an array of micro-mechanical display elements, each having a tiny mirror that is individually addressable by an electronic signal. Depending on the state of its addressing signal, each mirror tilts so that it either does or does not reflect light to the image plane, thereby modulating light incident on the DMD. The mirrors may be generally referred to as "display elements", which correspond to the pixels of the image that they generate. Generally, displaying pixel data is accomplished by loading memory cells connected to the display elements. Each memory cell receives one bit of data representing an on or off state of the display. The display elements can maintain their on or off state for controlled display times.
Other SLMs operate on similar principles, with an array of display elements that may emit or reflect light simultaneously, such that a complete image is generated by addressing display elements rather than by scanning a screen. Another example of an SLM is a liquid crystal display (LCD) having individually driven display elements.
For all types of SLMs, motion displays are achieved by updating the data in the SLM's memory cells at sufficiently fast rates. To achieve intermediate levels of illumination, between white (on) and black (off), pulse-width modulation (PWM) techniques are used. The basic PWM scheme involves first determining the rate at which images are to be presented to the viewer. This establishes a frame rate and a corresponding frame period. For example, if images are displayed 60 frames per second, each frame lasts for approximately 16.7 milliseconds. Then, the intensity resolution for each pixel is established. In a simple example, and assuming n bits of resolution, the frame time is divided into 2.sup.n -1 equal time slices. For a 16.7 millisecond frame period and n-bit intensity values, the time slice is 16.7/(2.sup.n -1) milliseconds.
Having established these times, for each pixel of each frame, pixel intensities are quantized, such that black is 0 time slices, the intensity level represented by the LSB is 1 time slice, and maximum brightness is 2.sup.n -1 time slices. Each pixel's quantized intensity determines its on-time during a frame period. Thus, during a frame period, each pixel with a quantized value of more than 0 is on for the number of time slices that correspond to its intensity. The viewer's eye integrates the pixel brightness so that the image appears the same as if it were generated with analog levels of light.
For addressing SLMs, PWM calls for the data to be formatted into "bit-planes", each bit-plane corresponding to a bit weight of the intensity value. Thus, if each pixel's intensity is represented by an n-bit value, each frame of data has n bit-planes. Each bit-plane has a 0 or 1 value for each display element. In the PWM example described in the preceding paragraphs, during a frame, each bit-plane is separately loaded and the display elements are addressed according to their associated bit-plane values. For example, the bit-plane representing the LSBs of each pixel is displayed for 1 time slice, whereas the bit-plane representing the MSBs is displayed for 2n/2 time slices.
Existing memories for storing data for delivery to the SLM have special purpose architectures. VRAM (video RAM) devices are row-addressable and can be combined with external logic for formatting. DMDRAM devices are ASICs having both data storage and format capability. An example of a DMDRAM is described in U.S. Pat. Ser. No. 08/333,199 (Atty Dkt No. TI-17869), entitled "Memory Architecture for Reformatting and Storing Display Data in Standard TV and HDTV Systems", assigned to Texas Instruments Incorporated.